The present invention relates to logical triggering, and more particularly to a channel-to-channel compare word recognizer for a logic analyzer.
In logic analyzers a word recognizer is a common triggering resource. As shown in FIG. 1 and in U.S. Pat. No. 4,823,076, an input digital signal having n logic channels, or n-bit words, is compared against a programmed m-bit reference value, where m<=n. The word recognizer output indicates whether the input digital signal, or selected channels thereof as determined by an n-bit mask value, matches the reference value. The reference value is static, i.e., the reference value is programmed before a data acquisition is started and is not reprogrammed while the data acquisition is ongoing.
For reliability issues some digital designs include redundant circuits. The redundant circuits run in parallel doing the same tasks, so both circuits should produce the same results. If the redundant circuits end up with different results, the designer needs to track down where the circuits diverged from each other.
On some wide digital buses the bit lines are broken into sections. The data on some of the sections may occur on different clock edges, but the logic analyzer ends up combining them into a single sample. When testing these buses, one test is to put redundant data on section 0 and section 2 and different redundant data on section 1 and section 3. Different data patterns are placed on the section pairs throughout the test. For each section pair the data patterns should always equal each other.
In the above two cases it is desired to compare input signal data channels against other data channels of the same input signal. Having a static programmed reference value for the word recognizer makes these problems impossible to solve.
What is desired is a means for comparing channels of data from an input signal with each other where the information on the compared channels is redundant.